FEATURES

•Single Power Supply Operation

- Low voltage range: 2.7 V - 3.6 V

•Memory Organization

- Pm25LD512C: 64K x 8 (512Kbit)

•Cost Effective Sector/Block Architecture

- 512Kb : Uniform 4KByte sectors / two uniform

32KByte blocks

•Low standby current 1uA (Typ)

•Serial Peripheral Interface (SPI) Compatible

- Supports single- or dual-output

- Supports SPI Modes 0 and 3 

- Maximum 33 MHz clock rate for normal read

- Maximum 100 MHz clock rate for fast read

•Page Program (up to 256 Bytes) Operation

- Typical 2 ms per page program

•Sector, Block or Chip Erase Operation

- Maximum 15ms sector, block or chip erase

•Low Power Consumption

- Typical 10 mA active read current

- Typical 15 mA program/erase current

•Hardware Write Protection

- Protect and unprotect the device from write

operation by Write Protect (WP#) Pin

•Software Write Protection

- The Block Protect (BP2, BP1, BP0) bits allowpartial or entire memory to be configured as read-only

•High Product Endurance

- Guaranteed 200,000 program/erase cycles per

single sector

- Minimum 20 years data retention

•Industrial Standard Pin-out and Package

- 8-pin 150mil SOIC

- 8-pin TSSOP

- 8-contact WSON

- Lead-free (Pb-free), halogen-free package